In standard silicon complementary metal oxide semiconductor (CMOS) technology, p-type field effect transistors (pFETs) use a boron (or other acceptor) doped p-type polysilicon layer as a gate electrode that is deposited on top of a silicon dioxide or silicon oxynitride gate dielectric layer. The gate voltage is applied through this polysilicon layer to create an inversion channel in the n-type silicon underneath the gate dielectric layer.
For a pFET to work properly, the inversion should begin occurring at slightly negative voltages applied to the polysilicon (poly-Si) gate electrode. This occurs as a consequence of the band alignment for the gate stack structure as depicted in FIG. 1. Specifically, FIG. 1 shows the approximate band alignment across a poly-Si/gate oxide gate stack in a typical pFET at zero gate bias. In FIG. 1, Ec, Ev and Ef are the conduction band edge, valence band edge and the Fermi level in the silicon, respectively. The poly-Si/gate oxide/n-type silicon stack forms a capacitor that swings into inversion at around 0 V and into accumulation around +1 V (depending on the substrate doping). The threshold voltage Vt, which can be interpreted as the voltage at which the inversion starts occurring, is therefore approximately 0 V and the flatband voltage, which is the voltage just beyond which the capacitor starts to swing into accumulation, is approximately +1 V. The exact values of the threshold and flatband voltages have a dependence on the doping level in the silicon substrate, and can be varied somewhat by choosing an appropriate substrate doping level.
In future technology, silicon dioxide or silicon oxynitride dielectrics will be replaced with a gate material that has a higher dielectric constant. These materials are known as “high k” materials with the term “high k” denoting an insulating material whose dielectric constant is greater than 4.0, preferably greater than about 7.0. The dielectric constants mentioned herein are relative to a vacuum unless otherwise specified. Of the various possibilities, hafnium oxide, hafnium silicate, or hafnium silicon oxynitride may be the most suitable replacement candidates for conventional gate dielectrics due to their excellent thermal stability at high temperatures.
Unfortunately, when p-type field effect transistors are fabricated using a dielectric such as hafnium oxide or hafnium silicate, it is a well known problem that the flatband voltage of the device is shifted from its ideal position of close to about +1 V, to about 0 +/−300 mV. This shift in flatband voltage is published in C. Hobbs et al., entitled “Fermi Level Pinning at the Poly-Si/Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers. Consequently, the threshold voltage of the device is shifted to approximately −1 V. This threshold voltage shift is believed to be a consequence of an intimate interaction between the Hf-based gate oxide layer and the polysilicon layer. One model (See, for example, C. Hobbs, et al., ibid.) speculates that such an interaction causes an increase in the density of states in the silicon band gap at the polysilicon-gate oxide interface, leading to “Fermi level pinning”. The threshold voltage therefore is not in the “right” place, i.e., it is too high for a useable CMOS (complementary metal oxide semiconductor) technology.
One possible solution to the above problem of threshold voltage shifting is by substrate engineering in which channel implants can be used to shift thresholds. Although substrate engineering is one possible means to stabilize threshold voltage shift, it can do so to a limited extent, which is inadequate for FETs that include a gate stack comprising a poly-Si gate electrode and a hafnium-containing high dielectric constant gate dielectric.
Another possible solution to the above problem of threshold voltage control in MOSFET has been disclosed in co-pending and co-assigned U.S. applicant Ser. Nos. 10/854,719, filed May 14, 2004 and 10/863,830, filed Jun. 4, 2004. In these two applications, a metal nitride containing material that may optionally include oxygen, such as Al(O)N, is used and it is positioned between a high k gate dielectric and a gate electrode.
In view of the above mentioned problem in threshold voltage and flatband voltage shift, it has been nearly impossible to develop a CMOS technology that is capable of stabilizing the threshold voltage and flatband voltage for such FETs. As such, a method and structure that is capable of stabilizing the threshold voltage and flatband voltage of FETs containing a gate stack is needed.